1. Field of the Invention
The present invention relates to a fabrication method of an interconnect. More particularly, the present invention relates to a fabrication method of the interconnect of an unlanded via.
2. Description of the Related Art
The multilevel interconnects structure is widely employed in the current manufacturing design for integrated circuits. In order to reduce the distance between the conductive linings at the same level, connections between the conductive linings at various levels are being made by means of an unlanded via technique. Although reducing the distance between the conductive linings increases the integration of an integrated circuit, having adjacent conductive linings separated by a dielectric layer, however, results in the formation of an undesired parasitic capacitor. The parasitic capacitance on a microelectronic device contributes to effects such as an increase of the RC delay time and a decrease in the operational speed of the device.
To mitigate the problem of the decreased operational speed of the device resulting from the parasitic capacitance, the dielectric layer between the conductive lining structures is formed from a material having a low dielectric constant. In general, the most common material used for the dielectric layer between the conductive lining structures is hydrogen silisesquoxane (HSQ).
FIGS. 1A to 1B are schematic, cross-sectional views illustrating various stages of the fabrication of the interconnect according to the conventional approach.
As shown in FIG. 1A, conductive lining structures 102 and an anti-reflection layer 104 are formed on a substrate 100. A first dielectric layer 106 is also formed to fill the opening 108 between the conductive lining structures 102. Materials used for the first dielectric layer 106 include the low dielectric constant material, hydrogen silsesquoxane. An isolation layer 110 is further formed to cover the first dielectric layer 106, followed by forming a second dielectric layer 112 to cover the entire substrate 100. A photoresist layer 114 with a specific pattern is further formed on the second dielectric layer 112. Anisotropic etching is then conducted to remove the second dielectric layer 112 to form a via opening 116 and to partially expose the antireflection layer 104.
According to the above approach, if the photoresist layer 114 is formed without being completely aligned with the conductive lining structures 102, a portion of the isolation layer 110 and the first dielectric layer 106 will be etched away during the anisotropic etching process. The first dielectric layer 106 is thus exposed. Furthermore, the first dielectric layer 106 is a hydrogen silsesquoxane layer, whose etching rate is faster than that of the second dielectric layer 112. A wider hole 118 is thus formed between the conductive lining structures 102 while forming the via opening 116.
Referring to FIG. 1B, after removing the photoresist layer 114 (as shown in FIG. 1A), a barrier layer 120 is formed on the surfaces of the via opening 116, followed by filling the via opening 116 with a metal layer 122. Material used for the metal layer 122 includes tungsten, and for the barrier layer 120 includes titanium nitride.
According to the above approach, the low dielectric constant hydrogen silsesquoxane is exposed when the via opening is formed. Since hydrogen silsesquoxane is very hygroscopic, if water vapor penetrates into the first dielectric layer, the polarity of water will increase the dielectric constant of the first dielectric layer. Furthermore, when forming the metal layer, the temperature for the tungsten deposition is about 400.degree. C. Under such a high temperature, the hydrated HSQ may exhibit out-gassing, which then hinders the metal layer from completely filling the via window and further leads to the occurrence of a poisoned via.